DISIT Lab of University of Florence | DISIT Lab of University of Florence

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DISIT Lab of University of Florence | DISIT Lab of University of Florence

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Title Validating Component Integration with C-TILCO, a Case Study

Subject formal speci¯cation language, ¯rst order logic, temporal interval logic, real-time systems, temporal operators, theorem provers, validation, components integration, communicating syste

Description Temporal logics are typically used to specify and verify properties and thus requirements, to describe the system and prove that such a formalization meets the expected behavior. In this paper, C-TILCO temporal logic is considered. C-TILCO is an extension of TILCO temporal logic which provides compositional and communication primitives. TILCO speci¯cations of system behavior can be directly used as implementations since they can be directly executed in real-time by using the TILCO executor. On the other hand, the validation phase remains of high relevance in the system deployment. The validation phase can be applied to both the single components and their integration in order to validate the entire solution. The validation requires dedicated tools to easily work out a considerable amount of proofs in reasonable time. To this end, in this article, a case study about speci¯cation of a communicating system is present

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